Parallel high-speed interfaces have strictly defined relative timing of their signals. This means that all data signals and associated clock (timing) signals (insofar as they exist) lie or are synchronized within a certain time window in order to ensure a correct acquisition of all data signals. Depending on this time window, which is defined for example by standardization or customer needs, the physical distribution of signals relevant as regards the timing is a dominating factor in maintaining the conditions of the time window and the synchronization conditions. At the same time, the timing definitions with regard to the time window may be negatively influenced if the corresponding signals pass through circuit blocks that influence the timing of the signals. Also, variations in the method for producing the high-speed interface, in which different sites of the high-speed interface may be variously affected, can further complicate the timing definitions with regard to synchronization of the signals to be made available by the high-speed interface.
Accordingly, expensive measuring devices are typically used in order to synchronize the signals of a parallel high-speed interface. Since the use of these measuring devices is not practicable on account of their mass production costs, it is customary to restrict a maximum data rate of a parallel high-speed interface so that the signals of the parallel high-speed interface can be transmitted correctly (i.e., without a misalignment between the signals leading to errors). In other words, it is normal practice to reduce the clock rate of a parallel high-speed interface until no errors with regards to the synchronization of its signals occur, and instead of improving the synchronization of the signals. This reduction of the clock rate obviously has a negative effect in terms of a lower overall throughput of a digital circuit that includes such a parallel high-speed interface.
For these and other reasons there is a need for the present invention.